Lesson · Problem 20
DAQ Capstone
One board, several disciplines
You should be able to
- Describe the capstone as power, analog, ADC, MCU, USB, and a four-layer stackup.
- Finish schematic checks before routing, and keep digital copper out of the analog keep-out.
Power · Analog · Mixed Signal · High-Speed Fundamentals · DFM / Manufacturing · Schematic Reasoning
What it is
The capstone has a schematic and a four-layer layout. Power, USB, the analog front end, and the MCU each keep earlier rules: decoupling, CC and ESD, pair skew and reference, keep-outs, test points, and design rules. The gain window is tighter than the earlier amplifier. The pass score still requires the published set, not a screenshot of one golden layout.
Why this matters
A data-acquisition board combines a connector, a regulator, analog conditioning, a converter, and a microcontroller. Each block can be right while the board is wrong.
What you are building
One four-layer board: connector and regulator, amplifier, ADC, MCU, and USB, starting from placed parts and an unwired schematic.
Prerequisites
This lesson uses linear regulator, dropout, non-inverting gain, low-pass, sampling, VREF, analog supply, digital supply, microcontroller, per-pin supply, SWD, D+, D−, CC pin, ESD, series resistor, differential pair, skew, reference plane, stackup, annular ring, drill, copper-to-edge, courtyard, DFM, return path. It introduces keep-out, subsystem review.
Component guide
What the parts are. The requirements panel is still the list that is graded.
Regulator A, B, and C
- What it does
- Three training linear regulators. Only one meets both the current and the dropout on the card.
- Why it is here
- The capstone asks you to choose from the card, not to memorize a letter.
- Symbol
- Three similar blocks. The card is the difference.
- Pins
- Input, output, ground.
- Constraints
- The passing part is both ≥ 0.2 A and ≤ 0.25 V dropout. One fails current. One fails dropout.
- Beginner mistake
- Picking the first regulator in the tray.
- What an engineer checks
- Dropout and rated current on each card.
ADC
- What it does
- The converter that turns the conditioned sensor voltage into a code against VREF.
- Why it is here
- AVDD, DVDD, and VREF each need the capacitor the card names, at that pin.
- Symbol
- The ADC block, with SPI leaving toward the MCU.
- Pins
- AIN, VREF, AVDD, DVDD, SCLK, MOSI, MISO, CS.
- Beginner mistake
- Treating VREF as the 3.3 V rail, or one capacitor for all three supplies.
- What an engineer checks
- Which capacitor is 100 nF and which is 1 µF, and the pin each one serves.
VREF
- What it does
- The ADC full-scale reference. Codes are fractions of this voltage.
- Why it is here
- The LDO tolerance is not the reference. The card states an ideal 3.300 V for the code check.
- Symbol
- A pin with a 1 µF capacitor to ground.
- Values
- 1 µF, routed within the distance the requirements state.
- Beginner mistake
- Using the input-filter capacitor, or the AVDD capacitor, on this pin.
- What an engineer checks
- The reference pin name and its capacitor.
AVDD and DVDD
- What it does
- Analog and digital supplies of the ADC. Each gets 100 nF at the pin.
- Why it is here
- They are different pins even when both sit near 3.3 V.
- Symbol
- Two supply pins, two capacitors, one ground pour.
- Beginner mistake
- A slot in ground between them.
- What an engineer checks
- The capacitor value and the maximum route length.
SWD
- What it does
- The debug pair, SWDIO and SWCLK, on the MCU.
- Why it is here
- Those nets are kept out of the analog keep-out, with the SPI and USB nets.
- Symbol
- Two nets on the MCU and the debug header.
- Pins
- SWDIO and SWCLK.
- Beginner mistake
- Routing them through the analog keep-out because it is shorter.
- What an engineer checks
- Pin names, and the keep-out the requirements name.
CC pins
- What it does
- The two USB-C configuration pins. Each gets its own 5.1 kΩ to ground.
- Why it is here
- A source detects the sink through those resistors.
- Symbol
- CC1 and CC2, each with a resistor.
- Values
- 5.1 kΩ, separate.
- Beginner mistake
- One resistor for both pins.
- What an engineer checks
- The resistor value on the card.
TVS and ESD
- What it does
- Clamps on the connector side of the USB data pair, to ground.
- Why it is here
- A clamp that is not on D+ or D− does not protect that pin.
- Symbol
- Shunt parts at the connector, before the pair runs across the board.
- Polarity
- The clamp faces the line the way the protection lesson drew it.
- Beginner mistake
- Leaving the ESD part off the data net.
- What an engineer checks
- Which channel connects to which polarity, and the ground pin.
Op-amp and sensor
- What it does
- The same non-inverting filter as the amplifier challenge, with a tighter gain window.
- Why it is here
- The sensor voltage is gained and filtered before the ADC.
- Symbol
- Op-amp, Rf, Rg, and the RC filter.
- Beginner mistake
- Mixing the filter capacitor with the op-amp’s supply capacitor.
- What an engineer checks
- The resistor ratio and the RC the requirements name.
Interview lens
Walk the blocks in order. For the regulator, use the card. For USB, name CC and the pair. For the ADC, separate VREF from the filter.
What PCBGrade measures
The same rules as the earlier challenges, with the tighter windows the brief states. No golden-layout screenshot and no USB compliance logo.
Where this shows up
A small DAQ board is these blocks on one stackup. A correct block can still fail the board.
Terms
- Capstone
- The last challenge. It combines earlier skills instead of introducing a new physical law.
- Keep-out
- A region where a class of copper or parts is not allowed.
What is happening electrically
This board measures a sensor and sends the result over USB. The physics is the physics of the earlier lessons, on one stack. The regulator has to hold 3.3 V inside its window. The amplifier sets gain and bandwidth. The converter samples against a reference, not against the regulator’s tolerance. The microcontroller needs a local capacitor at each supply pin, a defined reset, and a debug path. The USB pair is still a pair, with CC pins, series resistors, and ESD at the connector. The return for the fast nets is the L2 ground they face.
Why the geometry matters
Schematic checks come first. PCB layout stays locked until those checks pass, because copper cannot rescue a net that was never wired. On the board, keep the power loops short, the analog input away from the clock and the USB pair, and the pair over L2. The analog keep-out is a rectangle those digital nets must not enter. Coverage of L2 is how much of the outline is actually ground. Courtyards, test points, drill, and the edge are the build rules from the DFM lesson.
How an engineer reasons
Work by subsystem, in the order the requirements are grouped. Power, then the analog front end, then the ADC, then the MCU, then USB, then the stack and the ground, then the routes that connect them, then DRC and DFM. After each block, read the measured result against that block’s limits. A tidy picture of the whole board is not a substitute for a block you skipped. When two rules conflict on the copper, the keep-out and the reference are both real: dodging the keep-out by leaving L2 fails the reference.
Worked example
Start from the placed parts. Finish power and its capacitors, the USB pair and protection, and the MCU connections including test points. Keep SPI, the USB pair, and SWD copper out of the analog keep-out. The requirements panel splits schematic checks from layout checks.
Good and bad
A board that passes each subsystem’s checks is many valid layouts, not one golden picture. A board with a correct schematic and an unrouted pair is unfinished. A pair that looks equal by eye and dives off L2 to miss the analog keep-out fails two rules at once. A short from a supply to ground is not a layout style. It caps the result.
Common mistake
Leaving PCB Layout locked, or routing the USB pair off the ground reference to make the traces equal by eye.
Where this rule stops
Every number in the capstone is a published challenge limit. Some are tighter than the lesson that introduced the idea. None of them is a new physical law, and none of them is a field solution, a USB compliance test, or a claim that the coverage fraction is a solid return under every trace. The exact coordinate definitions and formulas stay collapsed on the challenge, under How PCBGrade measures this. Use them when you need the measurement. Use the subsystem list when you need to decide what to do next. Power, analog, ADC, MCU, USB, stackup, routing, and DFM are the blocks. A pass is the published set, not one picture of a finished board.
Before the challenge
The challenge combines the earlier blocks on one board. Read a subsystem, then the requirements under it. Schematic checks come first. The lesson does not walk the copper for you.
Ready for the challenge
You can name every new acronym on the sheet and say which lesson already taught that block.
Question 1 of 2