Finish a 4-layer data-acquisition board from the placed parts.
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Four-layer board, starting outline 48 × 30 mm. You may resize the rectangle up to 60 × 45 mm. The stack is fixed: L1 F.Cu signals, L2 In1.Cu GND, L3 In2.Cu power, L4 B.Cu signals. It is not a scored layer-count. The training USB-C symbol has no VBUS pin, so 5 V enters on JV. Regulator A is the only part that is both ≥ 0.2 A and ≤ 0.25 V dropout. B fails current. C fails dropout. The sweep is VIN 4.75–5.25 V × 0–200 mA and VOUT must stay in 3.20–3.40 V. That 200 mA is the regulator rating, not a USB power claim. CIN and COUT are each ≥ 1 µF. VIN to CIN and VOUT to COUT are ≤ 5.0 mm routed, and each ground terminal is also ≤ 5.0 mm routed from regulator GND. A pour does not count. Any of those four routed leads longer than 5.0 mm makes the sweep “not guaranteed.” The amplifier is the Problem 14 network: gain 3 is 2.97–3.03 (±1 %), 0.2 V maps to 0.594–0.606 V, and 1.0 V maps to 2.970–3.030 V. The op-amp is offset-free and clips at 0.10 V and 3.20 V. The sensor source is 0 Ω. Only 1.6 kΩ and 100 nF lands in 800–1200 Hz; 20 kΩ and 10 nF is 795.8 Hz. Feedback copper ≤ 20 mm. The 100 nF decoupler ≤ 4.0 mm on L1. ADC codes use ideal VREF 3.300 V, code = round(VIN / 3.300 × 4095), worst error ≤ 2 at 0.6 / 1.8 / 3.0 V (745 / 2234 / 3723). The LDO tolerance is not the reference. SPI at 8 MHz is on the card and is not graded. AVDD and DVDD 100 nF ≤ 4.0 mm, VREF 1 µF ≤ 5.0 mm, and the 47 Ω and 1 nF ≤ 5.0 mm, all routed, pours ignored. MCU VDD1, VDD2, and VDDA each match their own 100 nF within 4.0 mm (Problem 5). CC1 and CC2 are separate 5.1 kΩ resistors. Two 22 Ω series resistors. ESD and the series resistors are within 8.0 mm routed. Pair width is 0.20 mm within 0.005 mm, edge gap 0.18–0.22 mm, uncoupled ≤ 5.0 mm, skew ≤ 0.50 mm including barrels, ≤ 2 vias on each polarity. This is not 90 Ω and nothing enumerates. GND reference is the worse-net centreline fraction over L2, step 0.5 mm, ≥ 0.95. L2 coverage is anchored GND copper on In1 (pour plus GND traces, foreign-via antipads removed, floating islands ignored) divided by the outline polygon area, ≥ 0.85. In1 may carry only GND. In2 may carry only 3V3 and VBUS. Analog keep-out x 32–36 mm, y 3–6.5 mm: SCK, MOSI, MISO, CS, DP, DM, SWDIO, and SWCLK have 0 mm inside, on every layer. The boundary is outside. A short does not clear that length: copper declared on those nets is measured before the short removes the derived net. Courtyards of non-connectors stay ≥ 1.00 mm from the edge. Connectors are exempt. Test points on GND, 3V3, and NRST. DRC is the 2-layer set: clearance ≥ 0.20 mm, width ≥ 0.25 mm except the USB class at 0.20 mm and 0.18 mm inside the pair, via ≥ 0.60 / 0.30 mm, copper-to-edge ≥ 0.50 mm. Efficiency is 3 points of outline area (full at ≤ 1500 mm², none at 2700 mm²) and 2 points of total trace length (full at ≤ 1075 mm, none at 1720 mm). Vias are not length. A board that is incomplete, fails DRC, or puts a non-connector courtyard inside the 1.00 mm edge keepout gets 0 efficiency points, so a tiny unfinished outline cannot win. Rank order after the score is smaller outline area, then shorter trace length, with 0.01 mm² and 0.01 mm ties. Completion speed is not used. A VBUS–GND or 3V3–GND short, a missing or wrong regulator, or an unrouted DP, DM, or ADC SPI net caps the score at 69. That supply short still caps the score when the same copper also touches another net. Keep-out length is the centreline actually inside the rectangle, including a segment that crosses it or ends inside it. No SPICE, no LDO temperature, and no claim that 85 % coverage is a solid return path under the pair.
- schematic correctness · 20 pts
- power · 15 pts
- analog simulation · 15 pts
- ADC/digital · 10 pts
- PCB/layout · 25 pts
- DFM · 10 pts
- routing/area efficiency · 5 pts
- Cap 69: A VBUS–GND or 3V3–GND short, a missing or wrong regulator, or an unrouted DP, DM, or ADC SPI net caps the score at 69.
- Cap 69: Copper outside the outline cannot pass, and neither can a short between nets.
Reference
Regulator A
Passes 4.75–5.25 V in and 0–200 mA out. Dropout is a constant 0.25 V. Imax is 300 mA.
- 1. VIN. Input
- 2. GND. Ground
- 3. VOUT. Regulated output
Regulator B
Imax is 100 mA, so it cannot hold 3.3 V at 200 mA. Dropout is not stated and is not assumed.
- 1. VIN. Input
- 2. GND. Ground
- 3. VOUT. Regulated output
Regulator C
Imax is 300 mA, but dropout is a constant 2.0 V, so 4.75 V in cannot make 3.3 V out.
- 1. VIN. Input
- 2. GND. Ground
- 3. VOUT. Regulated output
TF-OPA1
Non-inverting use. V+ is 3.3 V. Output clips at 0.10 V and 3.20 V. GBW is 1 MHz. Vos is 0.
- 1. IN+. Non-inverting input
- 2. IN-. Inverting input
- 3. OUT. Output
- 4. V+. 3.3 V
- 5. V-. GND
TF-ADC12
code = round(VIN / 3.3 × 4095), clamped to 0..4095. SPI up to 8 MHz is not timed.
- 1. AIN. Analog input
- 2. AVDD. Analog supply
- 3. DVDD. Digital supply
- 4. VREF. 3.3 V reference
- 5. GND. Common ground
- 6. SCK. SPI clock
- 7. MOSI. SPI data in
- 8. MISO. SPI data out
- 9. CS. Chip select
TF-MCU32
Three supply pins, each with its own 100 nF. Active-low reset, SWD, one LED, one button.
- 1. VDD1. Digital supply. Own 100 nF to GND.
- 2. GND. Ground
- 3. VDD2. Digital supply. Own 100 nF to GND.
- 4. GND. Ground
- 5. VDDA. Analog supply. Own 100 nF to GND. No ferrite, no shared group.
- 6. NRST. Active-low reset. 10 kΩ to 3V3 and 100 nF to GND.
- 7. BOOT0. 10 kΩ pull-down to GND. A pull-up fails.
- 8. SWDIO. SWD data
- 9. SWCLK. SWD clock
- 10. LED_GPIO. Drives the LED high through 1 kΩ.
- 11. BUTTON_GPIO. Button to GND, 10 kΩ pull-up to 3V3.
- 12. NC. Not connected. Not graded.
USB-C receptacle
A6 and B6 are D+. A7 and B7 are D−. Each CC pin gets its own 5.1 kΩ to GND.
- 1. A6. D+
- 2. B6. D+
- 3. A7. D−
- 4. B7. D−
- 5. CC1. 5.1 kΩ to GND
- 6. CC2. 5.1 kΩ to GND
- 7. GND. Ground
TF-MCU FS
Internal D+ pull-up. Each USB line needs a 22 Ω series resistor. Driver impedance is not given a separate number.
- 1. VDD. 3.3 V
- 2. GND. Ground
- 3. DP. USB D+
- 4. DM. USB D−