Lesson · Problem 15
Connect an ADC
A converter has two worlds
You should be able to
- Give the reference, the analog supply, and the digital supply their own capacitors.
- Keep a clock out of the analog corridor without cutting the ground pour.
Mixed Signal · Analog · Grounding / Return Paths
What it is
Analog supply, digital supply, and the reference each get the capacitor the card names, at that pin. The input filter is a separate resistor and capacitor. Keep one solid ground pour. Separate analog and digital by placement and routing, not by cutting a gap in that pour.
An ADC reports a code against a reference, not against an abstract volt. Noise on VREF moves every code. A clock edge beside the analog input moves the sample. Cutting a slot in ground to “separate analog and digital” often forces return current around the slot, which is the opposite of a quiet measurement. Place the noisy nets away from the input and keep the pour continuous. This course grades that placement. It does not claim an ENOB or a lab noise floor.
Why this matters
An ADC compares an analog voltage to a reference. Digital edges nearby move the ground and the reference it is comparing against.
What you are building
An ADC with separate capacitors on AVDD, DVDD, and VREF, an input filter, and SPI kept out of the analog corridor.
Prerequisites
This lesson uses decoupling capacitor, low-pass, return path, reference plane, ground zone, microcontroller, net. It introduces sampling, VREF, analog supply, digital supply, input filter, split-ground caveat.
Component guide
What the parts are. The requirements panel is still the list that is graded.
ADC
- What it does
- Converts an analog voltage to a code by comparing it with a reference.
- Why it is here
- Noise on the reference moves every code. A clock beside the input moves the sample.
- Symbol
- A converter block with analog input, reference, and digital pins.
- Pins
- AIN, VREF, AVDD, DVDD, and the SPI pins.
- Beginner mistake
- Cutting a slot in ground to “separate analog and digital”.
- What an engineer checks
- Which capacitor belongs on VREF, AVDD, and DVDD. They are not interchangeable.
VREF
- What it does
- The reference voltage the converter treats as full scale.
- Why it is here
- The code is a fraction of VREF, not of an abstract volt.
- Symbol
- A pin with its own capacitor to ground.
- Values
- The capacitor the card names. It is not the input-filter capacitor.
- Beginner mistake
- Using the VREF capacitor as the signal filter.
- What an engineer checks
- The reference pin and its capacitor.
AVDD and DVDD
- What it does
- Analog supply and digital supply. Each is a pin with its own capacitor.
- Why it is here
- Digital edges should not share a capacitor symbol with the analog rail.
- Symbol
- Two supply pins, two capacitors, one continuous ground.
- Beginner mistake
- One capacitor tagged onto both names.
- What an engineer checks
- The value on each pin, at that pin.
Interview lens
VREF is full scale. A slot in ground is not how you separate analog and digital. Say both before you route.
What PCBGrade measures
Capacitor placement, the filter, corridor clearance, and one continuous ground. No ENOB and no lab noise floor.
Where this shows up
A converter whose codes jump when the clock runs is often a reference or a return, not a bad ADC.
Terms
- Reference
- The voltage the converter treats as full scale. It needs a quiet capacitor at the pin.
- Sampling
- The moment the converter compares the input with the reference and holds a code.
- Corridor
- A named region the SPI traces must stay out of. It is not a box the analog route is required to fill.
What is happening electrically
A converter compares the voltage at its input with a reference and reports a code. If the reference moves, every code moves. Sampling is that comparison, held for one conversion. The input network has to settle before the sample, which is why a resistor and capacitor in front of the pin are not optional decoration: they limit what the pin is asked to follow.
Analog and digital supplies inside one package feed different circuits. Each wants its own local capacitor. A digital edge, especially a clock, returns through ground. If that return shares a narrow path with the analog input or the reference, the sample moves. Cutting a slot in the ground to “separate analog and digital” often forces the return to walk around the slot, which couples the two sides more, not less.
Why the geometry matters
Place the capacitors the card names on AVDD, DVDD, and VREF, at those pins. Place the input resistor and capacitor as the filter, not as a substitute for the reference capacitor. Keep one continuous ground pour. Keep the clock and the other SPI traces out of the analog corridor by placement and routing. Do not route the clock beside the input because the trace is shorter.
How an engineer reasons
Ask what the code is relative to. It is relative to VREF, so quiet VREF is part of the measurement. Then ask what else moves at the sample instant. A clock edge is a suspect. Then ask where that edge’s current returns. A slot that looks like isolation is often a longer return. This course grades the placement and the corridor. It does not publish an ENOB or a lab noise floor.
Worked example
Place the stated capacitors on AVDD, DVDD, and VREF. Filter the input with the stated resistor and capacitor. Keep SPI traces out of the analog corridor. Coverage of the single ground pour is graded.
Good and bad
Separate capacitors, a real input filter, continuous ground, and SPI outside the corridor: the converter has a chance to measure the signal. One shared capacitor renamed onto three rails, or SCLK routed through the corridor, fails on purpose. A ground slot between “analog” and “digital” is not the repair.
Common mistake
Sharing one capacitor symbol across three supply names, or running SCLK through the analog corridor because it is shorter.
Where this rule stops
“Do not split the ground” is the right teaching rule on this board, where one solid pour and physical separation do the job. It is not a universal ban. Some systems use a split with a single, carefully placed bridge under the converter. A split without that return path is the common failure. The challenge grades the continuous pour and the corridor, not a claim about every mixed-signal product.
AVDD and DVDD are different supplies even on one package. Each capacitor belongs on the pin the card names. The reference capacitor is not the input filter, and the input filter is not a decoupler.
Before the challenge
The challenge has separate capacitors for the reference and the supplies, and a region the clock must stay out of. Do not cut the ground pour to make that separation.
Ready for the challenge
You can give each supply pin its own capacitor and keep SCLK out of the corridor.
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