15. Connect an ADC

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Problem 15

Wire the fixed amplifier output into TF-ADC12 and keep one L2 ground pour under the mixed-signal region.

Capacitors on AVDD, DVDD, and VREF, at those pins.
Keep SPI, including SCLK, out of the analog corridor.

Context

An ADC compares an analog voltage with a reference. Noise on the reference looks like noise on every code. AVDD, DVDD, and VREF each get their own capacitor. The input filter is a separate resistor and capacitor. Keep one ground pour. Do not cut a slot in it to “separate analog”.

Open the lesson Component guide

Components on this challenge

ADC. Converts an analog voltage to a code by comparing it with a reference.
VREF. The reference voltage the converter treats as full scale.
AVDD and DVDD. Analog supply and digital supply. Each is a pin with its own capacitor.

Complete the required schematic checks to unlock PCB Layout.

Full brief

Give the reference and each supply pin the capacitor the card names. Keep the clock out of the analog region without cutting a slot in the ground pour.

How PCBGrade measures this

Board 80 × 50 mm, four layers. J1 is the locked amplifier output from the Problem 14 reference: pin 1 is the ideal 0.6 V / 1.8 V / 3.0 V source and pin 2 is GND. The conversion does not include op-amp error. J3 pin 1 is 3V3 and pin 2 is GND. J2 is the locked SPI header. U1 is TF-ADC12 and is not locked. code = round(VIN / 3.3 × 4095), clamped to 0..4095. Round is half away from zero. 0.6 V is 745, 1.8 V is 2234, and 3.0 V is 3723. The worst absolute error must be ≤ 2 counts (32). SPI at 8 MHz is the card limit and is not graded. A 47 Ω resistor sits between the amplifier output and AIN, and a 1 nF sits from AIN to GND. Both the resistor’s AIN pad and the capacitor’s AIN pad must be within 5.0 mm routed of the AIN pin (3 each). 100 nF from 3V3 to GND within 4.0 mm routed of AVDD (5) and of DVDD (5). 1 µF from 3V3 to GND within 5.0 mm routed of VREF (5). Distances are pad centre to pad centre, zones excluded. AMP_REGION is x 0–18 mm, y 8–40 mm. MCU_REGION is x 62–80 mm, y 8–40 mm. Facing uses the AIN pad vector and the SCK pad vector from the body centre. Each must be within 45° of the direction to that region’s centroid (2 each). ANALOG_CORRIDOR is x 20–34 mm, y 16–32 mm. SPI traces (SCK, MOSI, MISO, CS) stay out of it on every layer (4). Touching the boundary passes. A centreline that enters fails. One connected L2 GND pour (4). Pours that touch or overlap count as one. MIXED is x 4–76 mm, y 4–46 mm. L2 GND coverage of that rectangle is ≥ 0.95 (3), the same anchored-rectangle measure as Problem 11, including a non-GND via anti-pad only when the via’s box sits fully inside a counted rectangle. L2 is the ground layer. An unrouted net or a conversion that misses the ±2 count window caps the score at 60. DRC is clearance 0.20 mm, width 0.25 mm, and copper-to-edge 0.50 mm.

connectivity/function · 35 pts
supply/reference handling · 25 pts
partitioning/layout · 25 pts
DRC · 15 pts
Cap 60: A conversion outside ±2 counts, or an unrouted net, caps the score at 60.
Cap 69: Copper outside the outline cannot pass, and neither can a short between nets.

Reference

TF-ADC12

code = round(VIN / 3.3 × 4095), clamped to 0..4095. SPI up to 8 MHz is not timed.

1. AIN. Analog input
2. AVDD. Analog supply
3. DVDD. Digital supply
4. VREF. 3.3 V reference
5. GND. Common ground
6. SCK. SPI clock
7. MOSI. SPI data in
8. MISO. SPI data out
9. CS. Chip select

Schematic · Drag a part. Drag empty sheet to pan. Scroll to zoom.

Pass at 70. Check previews. Submit records.

Schematic5

AVDD valueNot checked
Scored · 3 pts
AVDD uses 100 nF, not the 1 µF reference capacitor.
DVDD valueNot checked
Scored · 3 pts
DVDD uses its own 100 nF.
VREF valueNot checked
Scored · 4 pts
VREF uses 1 µF.
47 ΩNot checked
Scored · 2 pts
The series resistor is 47 Ω. 4.7 Ω and 470 Ω are the traps.
1 nFNot checked
Scored · 2 pts
The shunt is 1 nF.

Stackup1

MIXED coverageNot checked
Scored · 3 pts
The L2 GND pour covers at least 95 % of the mixed-signal rectangle.

Routing10

ConnectivityNot checked
Scored · 3 pts
Every net has to be routed, with no shorts.
AVDD capacitorNot checked
Scored · 5 pts
The 100 nF 3V3 pad stays within 4.0 mm of AVDD.
DVDD capacitorNot checked
Scored · 5 pts
A second 100 nF stays within 4.0 mm of DVDD.
VREF capacitorNot checked
Scored · 5 pts
The 1 µF 3V3 pad stays within 5.0 mm of VREF.
Filter resistorNot checked
Scored · 3 pts
The 47 Ω pad on AIN stays within 5.0 mm of the AIN pin.
Filter capacitorNot checked
Scored · 3 pts
The 1 nF pad on AIN stays within 5.0 mm of the AIN pin.
One GND pourNot checked
Scored · 4 pts
L2 GND is one connected pour. A gap between pours is a split, even when both are GND.
Analog facingNot checked
Scored · 2 pts
The AIN pad points within 45° of AMP_REGION.
SPI facingNot checked
Scored · 2 pts
The SCK pad points within 45° of MCU_REGION.
SPI stays out of the analog corridorNot checked
Scored · 4 pts
SPI traces stay out of ANALOG_CORRIDOR. The boundary itself passes.

DRC1

DRCNot checked
Scored · 15 pts
Clearance, width, and the board edge apply on every copper layer.

Requirements1

Conversion errorNot checked
Scored · 32 pts
The worst of 745, 2234, and 3723 must stay within 2 counts.

PCBGrade

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