Problem 19
Repair five root causes on a malfunctioning MCU, USB, and ADC board, and match each authored panel to its cause.
Debugging objective
- Read each panel before changing a part.
- The board still has to connect and pass design rules after the repair.
Context
The panels under Reference are measurements of the faulty prototype. They do not update when you edit, and they are not a live oscilloscope. Use them as evidence. Infer the cause, then repair it. The exact measurement method is under How PCBGrade measures this.
Evidence
Panel 1 — VDD during a load step
Reference measurement of the faulty prototype. VDD collapses during the load step. Not a measurement of your board.
Authored evidence. This panel does not update when you edit.
Panel 2 — NRST glitch
Reference measurement of the faulty prototype. NRST glitches while VDD stays steady. Not a measurement of your board.
Authored evidence. This panel does not update when you edit.
Panel 3 — USB attach
Reference measurement of the faulty prototype. The host records a low-speed attach. Not a measurement of your board.
Authored evidence. This panel does not update when you edit.
Panel 4 — code error versus input
Reference measurement of the faulty prototype. The code error grows with the input and lines up with conversions. Not a measurement of your board.
Authored evidence. This panel does not update when you edit.
Panel 5 — ADC noise
Reference measurement of the faulty prototype. The noise is synchronous with SCLK and does not grow with the input. Not a measurement of your board.
Authored evidence. This panel does not update when you edit.
Components on this challenge
- Authored evidence. Measurements written for the faulty prototype. They do not update when you edit.
- Capacitor. Stores charge and supplies a short pulse of current. With a resistor it also sets a time.
- USB pair on this board. D+ and D− through the connector, the series resistors, and the ESD parts.
Complete the required schematic checks to unlock PCB Layout.
Full brief
A two-layer board, 140 × 90 mm, is already built and it misbehaves. U32 is TF-MCU32, UFS is TF-MCU-FS, and UADC is TF-ADC12. The five panels under Reference are measurements of that faulty prototype. They do not change when you edit.
Read those symptoms and repair the five causes they imply. Each cause is 15 points and all-or-nothing. Matching a panel to its cause is 2 points. Connectivity and the design rules are 15 points, and they pass only when clearance, width, drill, via size, and copper-to-edge are all clean. Two unrepaired causes cannot pass. The pass line is 70.
How PCBGrade measures this
Each cause is all-or-nothing. Final connectivity is your copper against your own schematic, plus DRC (clearance ≥ 0.20 mm, width ≥ 0.25 mm, drill ≥ 0.30 mm, via ≥ 0.60 mm, copper-to-edge ≥ 0.50 mm). Score = 15k + 15c + e. A board with only three causes repaired, clean copper, and every panel correct would be 70. That is capped at 69 unless at least four of the five causes are repaired. RC1: role bulk, total capacitance between 3V3 and GND ≥ 10 µF. Leaving the 0.1 µF and adding 10 µF in parallel counts. RC2: exactly 10 kΩ between NRST and U32’s 3V3. 4.7 kΩ and 22 kΩ fail. A pull-up to VBUS or GND fails. Keep the 100 nF from NRST to GND. RC3: UFS DP through one 22 Ω to the net that joins ESD IO1, A6, and B6, and DM through one 22 Ω to ESD IO2, A7, and B7. Schematic and copper both have to match. Labels without the copper, or copper without the labels, score 0 for this cause. The 22 Ω value is exact: 21 Ω and 23 Ω fail. RC4: ≥ 1 µF from VREF to GND, and the capacitor pin on VREF within 5.0 mm routed of UADC VREF. Any capacitor of that role counts. The pin is whichever pin is on VREF, not a fixed reference or pin number. 10 nF fails. 1 µF at 20 mm fails. A pour does not count as the route. RC5: SCLK centreline length inside ANALOG (x 90–99 mm, y 46–54 mm) ≤ 0. The boundary is outside, so a run that lies on the edge measures 0. A segment that crosses the rectangle, and a stub that ends inside it, count the length that is actually inside. On this 1.6 mm two-layer board the coupling limit is an in-plane edge gap of 3.0 mm on every layer (k ≈ 0.18, not a field solution), so SCLK on the back directly under AIN is close. SCLK length closer than 3.0 mm to AIN must be ≤ 3.0 mm, which allows a short crossing. A 0.26 mm nudge or a 24.9 mm trim of the seeded 25 mm run does not repair RC5. No eye diagram, no crosstalk voltage, and no claim that USB enumerates.
- correctly repaired root causes (15 points each × 5) · 75 pts
- final connectivity/DRC · 15 pts
- evidence-to-cause reasoning · 10 pts
- Cap 69: Fewer than four repaired causes caps the score at 69.
- Cap 69: Copper outside the outline cannot pass, and neither can a short. The one exception is a D+ to D− short whose labels are already repaired and whose series copper is still swapped.
Reference
TF-MCU32
Three supply pins, each with its own 100 nF. Active-low reset, SWD, one LED, one button.
- 1. VDD1. Digital supply. Own 100 nF to GND.
- 2. GND. Ground
- 3. VDD2. Digital supply. Own 100 nF to GND.
- 4. GND. Ground
- 5. VDDA. Analog supply. Own 100 nF to GND. No ferrite, no shared group.
- 6. NRST. Active-low reset. 10 kΩ to 3V3 and 100 nF to GND.
- 7. BOOT0. 10 kΩ pull-down to GND. A pull-up fails.
- 8. SWDIO. SWD data
- 9. SWCLK. SWD clock
- 10. LED_GPIO. Drives the LED high through 1 kΩ.
- 11. BUTTON_GPIO. Button to GND, 10 kΩ pull-up to 3V3.
- 12. NC. Not connected. Not graded.
TF-MCU FS
Internal D+ pull-up. Each USB line needs a 22 Ω series resistor. Driver impedance is not given a separate number.
- 1. VDD. 3.3 V
- 2. GND. Ground
- 3. DP. USB D+
- 4. DM. USB D−
TF-ADC12
code = round(VIN / 3.3 × 4095), clamped to 0..4095. SPI up to 8 MHz is not timed.
- 1. AIN. Analog input
- 2. AVDD. Analog supply
- 3. DVDD. Digital supply
- 4. VREF. 3.3 V reference
- 5. GND. Common ground
- 6. SCK. SPI clock
- 7. MOSI. SPI data in
- 8. MISO. SPI data out
- 9. CS. Chip select