Problem 18
Repair ten seeded manufacturing issues on a board that already works electrically.
- Repair the seeded issues without breaking connectivity.
- Read the measured value on the failed rule before dragging parts.
Context
A board can be electrically right and still be hard to build. This challenge seeds specific issues: silk on pads, parts too close, copper near the edge, a small drill, a narrow trace, missing test points, and a polarity mark on the wrong side. Annular ring is the copper around a hole. Enlarging a pad does not fix a drill that is too small.
Components on this challenge
- Annular ring. The copper donut left around a drilled hole.
- Courtyard. The keep-out around a footprint so parts and the board edge stay clear.
Full brief
The board is already connected and already contains build defects. Repair the defect named by the failed check. Shifting every part by the same amount is not a repair.
How PCBGrade measures this
Board 50 × 40 mm, two layers. The starter already connects 3V3 through the 330 Ω resistor and the LED to GND, and RESET is routed. It also contains all ten defects: a GND spur 0.49 mm from the outline, R2 and R3 courtyards overlapping, silk across the LED pad, a 0.20 / 0.60 mm via, a 0.15 mm RESET trace, R4’s courtyard inside the 1.00 mm edge keep-in, no test points, and the polarity mark on the anode side. J1, J2, R1, and D1 are locked. Do not delete them or change their footprints. R2, R3, R4, the silk mark, and the polarity mark may move. The outline and the design rules are fixed. Each seeded issue is 8 points. Final compliance is 20 points and is all-or-nothing: any one remaining seeded issue, or any new violation of the same checks, scores that 20 as 0. Nine repairs and one leftover is 72 and passes. Eight repairs is 64 and fails. 70 is not a possible score. An open or shorted net caps the score at 60. The ten issues are: copper-to-edge ≥ 0.50 mm from the copper edge; courtyard overlap area 0 (touching passes, same side only); silkscreen stroke versus exposed pad overlap area 0; via drill ≥ 0.30 mm (enlarging the seeded 0.20 mm drill to 0.30 mm on the 0.60 mm pad leaves a 0.15 mm ring); trace width ≥ 0.25 mm; non-connector courtyard to the board edge ≥ 1.00 mm (connectors are exempt); a test-point footprint on GND, on 3V3, and on RESET (a via does not count); and a polarity mark closer to the LED cathode (pin 2) than the anode, within 1.5 mm of the cathode pad edge. The palette allows four test points. One on each required net is enough, and a second one on the same net still passes. The mark is the cathode convention. The editor places vias at 0.60 / 0.30 mm. There is no separate score for test-point size. Courtyard-to-edge measures the courtyard outline against the board outline. A courtyard that crosses the edge fails even when every corner is still 1 mm from the edge line.
- repaired seeded issues (8 points each × 10) · 80 pts
- final DRC/manufacturing-rule compliance · 20 pts
- Cap 60: An open or shorted net caps the score at 60.
- Cap 69: Copper outside the outline cannot pass, and neither can a short between nets.
Reference
Training LED
Conducts at a fixed 2.0 V drop when forward-biased. Current is (Vsupply − 2.0 V) / R in a series circuit.