Problem 13
Terminate USB-C CC pins, join the duplicate data contacts, and route the pair over L2 ground.
- Join both D+ contacts and both D− contacts.
- Fit the CC resistors and the ESD parts. Route the pair over ground.
Context
USB-C repeats the USB 2.0 data pads. Both D+ pads are one net, and both D− pads are one net. Each CC pin gets the 5.1 kΩ pull-down the card names. ESD is a shunt from the data line to ground, on the connector side.
Components on this challenge
- USB-C receptacle. The connector repeats the USB 2.0 data pins and adds CC pins.
- CC pin. Configuration Channel. A pull-down tells a USB-C source that a sink is attached.
- ESD diode. A clamp from a data net to ground at the connector.
Complete the required schematic checks to unlock PCB Layout.
Full brief
Join both D+ contacts, join both D− contacts, and give each CC pin its own resistor to ground. Route the pair over the ground reference.
How PCBGrade measures this
J1 is a locked USB-C receptacle and U1 is a locked full-speed training MCU on an 80 × 40 mm four-layer board. J1 pins are A6 D+, B6 D+, A7 D−, B7 D−, CC1, CC2, and GND. U1 is VDD, GND, DP, and DM. The MCU card has an internal D+ pull-up. Each line needs one 22 Ω series resistor. There is no protocol emulator and no impedance calculation. CC1 and CC2 each need their own 5.1 kΩ resistor to GND. 4.7 kΩ and 5.6 kΩ are not the specified 5.1 kΩ; they are not described as undetectable. Tie A6 to B6, and A7 to B7. The ESD array sits on the connector side of the 22 Ω resistors, with its ground pin on GND. Pair geometry is the connector-side nets DP and DM only (receptacle, ESD, and the resistor pin on that side). The MCU-side nets are ordinary routes and are not in the pair length. Width is 0.20 mm within 0.005 mm (8). A parallel run is the same 1° and 1.0 mm definition as Problem 12, and the edge gap is rounded to 0.001 mm. Every such run is from 0.18 mm to 0.22 mm (5 each). Uncoupled length on the worse polarity is ≤ 5.0 mm (2), borrowed so the pair cannot pass by staying apart. Skew is the absolute difference of those two nets’ centreline lengths plus 1.565 mm barrels, and it is ≤ 0.50 mm (4). Stubs are included. GND reference is the centreline fraction over L2, sampled every 0.5 mm, worse net ≥ 0.95 (4). Continuous means no interior reference-gap crossing (2). L4 looks at L3, which is not GND. Each polarity, connector-side net plus MCU-side net, may have at most 2 vias (4). ESD pad centre to the farther receptacle contact of that polarity is ≤ 8.0 mm of copper (5 each). Each series resistor’s MCU-side pad to the MCU pin is ≤ 8.0 mm (5 each). An open path fails that check. The pair class sets width 0.20 mm and intra-pair clearance 0.18 mm. Other copper stays at 0.25 mm width and 0.20 mm clearance. DRC is 6 and connectivity is 5. A missing or shared CC resistor, a CC or series value other than 5.1 kΩ or 22 Ω, a D+ or D− join that is missing or shorted, an ESD pin off its net, or an unrouted net caps the score at 60.
- schematic · 35 pts
- pair routing · 30 pts
- protection/component placement · 20 pts
- DRC · 15 pts
- Cap 60: A wrong or missing CC or series value, a broken D+ or D− join, an ESD pin off its net, or an unrouted net caps the score at 60.
- Cap 69: Copper outside the outline cannot pass, and neither can a short between nets.
Reference
TF-MCU FS
Internal D+ pull-up. Each USB line needs a 22 Ω series resistor. Driver impedance is not given a separate number.
- 1. VDD. 3.3 V
- 2. GND. Ground
- 3. DP. USB D+
- 4. DM. USB D−
USB-C receptacle
A6 and B6 are D+. A7 and B7 are D−. Each CC pin gets its own 5.1 kΩ to GND.
- 1. A6. D+
- 2. B6. D+
- 3. A7. D−
- 4. B7. D−
- 5. CC1. 5.1 kΩ to GND
- 6. CC2. 5.1 kΩ to GND
- 7. GND. Ground
USB ESD array
Two IO channels and GND. Place it on the connector side of the 22 Ω resistors.