11. Move to Four Layers

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WidthNetLayer

Problem 11

Route the MCU power and SWD nets on a four-layer board with an L2 ground pour.

Ground pour on L2. The next inner layer is for 3.3 V, not for signals.
Via the MCU ground pins into L2. SWD stays over that reference.

Context

A stackup is the ordered copper and dielectric. In this course the signal on top should face ground on the next copper layer. A via is how a ground pin reaches that plane. A schematic ground symbol does not fill the layer.

Open the lesson Component guide

Components on this challenge

Stackup. The ordered copper layers. This course uses signal, ground, power, signal.

Full brief

Signals on L1 face ground on L2. Power is the next inner layer. Via the ground pins into that ground layer. A ground symbol does not pour copper.

How PCBGrade measures this

Board 50 × 40 mm, four layers. L1 (F.Cu) is components and signals. L2 (In1.Cu) is GND only. L3 (In2.Cu) is 3V3 only. L4 (B.Cu) may carry signals. There is no 5 V net, and no slow net is on the L3 allow-list. J1, U1, and J2 are locked. J1 pin 1 is 3V3 and pin 2 is GND. J2 is 3V3, GND, SWDIO, SWCLK. U1 pins 1, 3, and 5 are 3V3. Pins 2 and 4 are GND. Pin 8 is SWDIO and pin 9 is SWCLK. Other MCU pins are not on a net. This slice does not grade the Problem 5 decoupler distance. A via is 0.60 / 0.30 mm. A full F.Cu to B.Cu barrel is 1.565 mm and is not added to the fast-net reference length. Usable area is the outline inset by the 0.50 mm copper-to-edge rule: 49 × 39 mm. L2 GND coverage is the area of anchored GND pour rectangles on L2, plus axis-aligned GND traces on L2, clipped to that rectangle, divided by 1911 mm². A pour counts only when a GND via or GND pad sits inside it. A non-GND via whose anti-pad box (radius = via radius + 0.20 mm) lies fully inside a counted rectangle is subtracted as πr². Through-hole pads are not cut out. Diagonal L2 traces are not added. The requirement is ≥ 0.85 (18 points). Each MCU GND pin must reach a GND via within 3.0 mm routed along L1 copper, measured to the via centre. The via must span L2 and its centre must lie inside an L2 GND pour. The grade uses the worse pin (12 points). Fast nets are SWDIO and SWCLK. Ground beneath is the centreline fraction over L2 GND, sampled every 0.5 mm. L1 looks at L2. L4 looks at L3, and only GND copper there counts, so an L4 fast net over a 3V3 plane scores 0. The worse net must be ≥ 0.95 (20 points). A gap that the centreline leaves and re-enters is not a separate score. A slot can still pass 0.95. Layer usage (25) counts L2 or L3 traces and pours whose net is not on that layer’s list. Vias are not traces. Connectivity is 10 and DRC is 10 (clearance 0.20 mm, width 0.25 mm, copper-to-edge 0.50 mm, including the inner layers). An unnecessary via (5) is one that touches its net’s copper on fewer than two layers, or a non-plane via whose spanned layers are already spanned by another via of the same net. Plane nets are GND and 3V3. There is no extra score cap.

layer usage · 25 pts
plane quality · 30 pts
reference continuity · 20 pts
connectivity/DRC · 20 pts
unnecessary vias · 5 pts
Cap 69: Copper outside the outline cannot pass, and neither can a short between nets.

Reference

TF-MCU32

Three supply pins, each with its own 100 nF. Active-low reset, SWD, one LED, one button.

1. VDD1. Digital supply. Own 100 nF to GND.
2. GND. Ground
3. VDD2. Digital supply. Own 100 nF to GND.
4. GND. Ground
5. VDDA. Analog supply. Own 100 nF to GND. No ferrite, no shared group.
6. NRST. Active-low reset. 10 kΩ to 3V3 and 100 nF to GND.
7. BOOT0. 10 kΩ pull-down to GND. A pull-up fails.
8. SWDIO. SWD data
9. SWCLK. SWD clock
10. LED_GPIO. Drives the LED high through 1 kΩ.
11. BUTTON_GPIO. Button to GND, 10 kΩ pull-up to 3V3.
12. NC. Not connected. Not graded.

Trace · pour outline · ratsnest · Drag a part or via. Drag a trace end to edit it. Drag empty board to pan.

Pass at 70. Check previews. Submit records.

MCU2

MCU GND viasNot checked
Scored · 12 pts
Each ground pin needs a short path onto the L2 pour.
SWD referenceNot checked
Scored · 20 pts
SWDIO and SWCLK need L2 ground under the centreline. L4 would be looking at L3, which is not GND.

Stackup2

Plane allow-listNot checked
Scored · 25 pts
L2 is the ground plane and L3 is the 3V3 plane. A signal track there breaks the stackup.
L2 GND coverageNot checked
Scored · 18 pts
The ground pour has to cover the usable board. Coverage does not prove the pour is continuous.

Routing2

ConnectivityNot checked
Scored · 10 pts
Power and SWD still have to be routed.
Unnecessary viasNot checked
Scored · 5 pts
A via that does not change layers, or a second signal via across the same layers, is not doing work.

DRC1

DRCNot checked
Scored · 10 pts
Clearance, width, and the board edge apply on every copper layer.

PCBGrade

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