7. Give Current a Return Path

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Problem 7

Route three fast signals over a B.Cu GND zone and keep them out of the void.

Keep the fast nets over the back-side ground and out of the void.
A detour around the void is expected. A detour that is too long still fails the length limit.

Context

Current that leaves on a trace returns on the lowest-inductance copper, which for a fast edge is the ground under the trace. A void is a hole in that pour. Crossing it makes the loop larger even when the trace looks short.

Open the lesson Component guide

Components on this challenge

Return path. The copper the current uses to come back, usually ground under the signal.

Full brief

Keep the fast traces over the ground pour and out of the void. A short trace across that hole still has a long return.

How PCBGrade measures this

Board 50 × 30 mm, two layers. The test points are locked. Route SIG1, SIG2, and SIG3 on F.Cu. The starter B.Cu GND zone is 40 × 25 mm (1000 mm²). This is a geometry check, not EMI simulation. Coverage samples each trace at the middle of every 0.5 mm cell, including a shorter last cell. A cell counts only when the centre and both edges of the trace width lie on B.Cu GND copper or inside the GND zone, and not inside the ground void or on other B.Cu copper. A trace drawn on B.Cu is uncovered. Vias add no length. Each trace needs at least 0.95 of its own length (6 points each). Crossing the void is 32 points, all or nothing, so a crossing scores at most 68. Touching the void outline passes; entering it fails. The check follows the whole trace centreline, not only the endpoints. Length is 5 points per trace: routed length at most 1.5× the octilinear span of the pad centres, and at most 2 vias. Octilinear length is max(dx, dy) + (√2 − 1)·min(dx, dy). The zone area must stay at least 0.95 of 1000 mm² (10 points). Overlapping zones are not unioned. Connectivity is 15 and DRC is 10. There is no extra cap.

reference continuity · 50 pts
connectivity/DRC · 25 pts
route length efficiency · 15 pts
ground-plane integrity · 10 pts
Cap 69: Copper outside the outline cannot pass, and neither can a short between nets.

Trace · pour outline · ratsnest · Drag a part or via. Drag a trace end to edit it. Drag empty board to pan.

Pass at 70. Check previews. Submit records.

Stackup3

SIG1 coverageNot checked
Scored · 6 pts
Each fast trace is sampled on its own. One well-covered trace does not hide another.
SIG2 coverageNot checked
Scored · 6 pts
Each fast trace is sampled on its own. One well-covered trace does not hide another.
SIG3 coverageNot checked
Scored · 6 pts
Each fast trace is sampled on its own. One well-covered trace does not hide another.

Routing6

Keep traces out of the ground voidNot checked
Scored · 32 pts
Copper that enters the void has no return directly beneath it. Touching the outline is allowed.
ConnectivityNot checked
Scored · 15 pts
Each pair still has to be one copper net.
SIG1 lengthNot checked
Scored · 5 pts
Detour around the void is expected. A route much longer than the pads is not.
SIG2 lengthNot checked
Scored · 5 pts
Detour around the void is expected. A route much longer than the pads is not.
SIG3 lengthNot checked
Scored · 5 pts
Detour around the void is expected. A route much longer than the pads is not.
GND zone areaNot checked
Scored · 10 pts
Shrinking the return zone is not a way to dodge the void. The check is area only.

DRC1

DRCNot checked
Scored · 10 pts
Clearance and the board edge still apply.

PCBGrade

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