6. Choose the Right Trace

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WidthNetLayer

Problem 6

Route SIGNAL, AUX, and POWER at the widths the brief states. Currents are context only.

SIGNAL at least 0.25 mm, AUX at least 0.50 mm, POWER at least 1.00 mm, on every segment.
Clearance is 0.20 mm. Copper stays at least 0.50 mm from the board edge.

Context

Trace width is the drawn width of the copper. A wider trace is used here because the brief assigns that net a higher current. You are graded on the stated minimum, not on a calculator of your own.

Open the lesson Component guide

Components on this challenge

Trace. A strip of copper of a stated width on a stated layer.

Full brief

Route every segment of SIGNAL at least 0.25 mm, AUX at least 0.50 mm, and POWER at least 1.00 mm. A connected trace that is narrower than its net still fails.

How PCBGrade measures this

The connectors are locked on a 40 × 30 mm board. Route pin 1 of each pair; pin 2 is unused. SIGNAL (20 mA) is at least 0.25 mm, AUX (500 mA) at least 0.50 mm, and POWER (1.5 A) at least 1.00 mm, on every segment. Those currents and the 35 µm copper resistivity are context and are not scored. POWER is 35 points, AUX 15, and SIGNAL 10, so a thin POWER trace scores at most 65 and does not pass. There is no separate critical-error cap. Connectivity is 15 and DRC is 10 (clearance 0.20 mm, copper at least 0.50 mm from the edge). Excess is 5 points per net: routed length at most 1.5× the octilinear span of the pad centres, and at most 2 vias on that net. Octilinear length is max(dx, dy) + (√2 − 1)·min(dx, dy). A via counts as one instance. Pours are not allowed.

width compliance · 60 pts
connectivity/DRC · 25 pts
unreasonable excess length/vias · 15 pts
Cap 69: Copper outside the outline cannot pass, and neither can a short between nets.

Trace · ratsnest · Drag a part or via. Drag a trace end to edit it. Drag empty board to pan.

Pass at 70. Check previews. Submit records.

Routing7

SIGNAL widthNot checked
Scored · 10 pts
Every segment of the net is measured. The current figure is context; it is not a graded resistance.
AUX widthNot checked
Scored · 15 pts
Every segment of the net is measured. The current figure is context; it is not a graded resistance.
POWER widthNot checked
Scored · 35 pts
Every segment of the net is measured. The current figure is context; it is not a graded resistance.
ConnectivityNot checked
Scored · 15 pts
Each pair still has to be one copper net.
SIGNAL excessNot checked
Scored · 5 pts
A route much longer than the octilinear span, or a pile of vias, is not this challenge.
AUX excessNot checked
Scored · 5 pts
A route much longer than the octilinear span, or a pile of vias, is not this challenge.
POWER excessNot checked
Scored · 5 pts
A route much longer than the octilinear span, or a pile of vias, is not this challenge.

DRC1

DRCNot checked
Scored · 10 pts
Clearance and edge copper still have to meet the board rules.

PCBGrade

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