3. Route Your First PCB

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WidthNetLayer

Problem 3

Place the connectors in their zones and route the TF-BUF5 board without shorts or design-rule errors.

Place the connectors in their zones.
Route every net, including power, ground, and the LED.
Copper of different nets must not touch. Stay inside the outline.

Context

A schematic net does not carry current across a board. A ratsnest is a dashed guide. A trace is solid copper with a width. A via joins layers. A footprint is the copper and holes for a part; a pad is one connection on that footprint.

Open the lesson Component guide

Components on this challenge

Footprint and pad. The footprint is the part on the board. A pad is one pin of that footprint.
LED. A diode that emits light when current flows from anode to cathode.
Resistor. Limits current. The voltage across it divided by its resistance is the current through it.

Full brief

Place the parts and route every net in copper. A ratsnest is not a connection. Keep the input connector in the left zone and the output connector in the right zone.

How PCBGrade measures this

The schematic is already decided: J1 brings in 3V3, IN, and GND; U1 is a TF-BUF5; C1 is 100 nF; R1 and D1 are the output LED; J2 is the output connector. Move the parts onto the 35 × 25 mm board, put J1’s pads in the left zone and J2’s pads in the right zone, and route every net on the top layer. Vias are allowed (0.60 / 0.30 mm, not editable) but a short top-layer route scores better. There is no copper pour.

connectivity/completeness · 35 pts
DRC · 30 pts
placement constraints · 20 pts
routing/via efficiency · 15 pts
Cap 60: A short or an unrouted net caps the score at 60.
Cap 69: Copper outside the outline cannot pass, and neither can a short between nets.

Reference

TF-BUF5

Single buffer. OUT follows IN only when VCC is powered and EN_N is low.

1. IN. Input
2. GND. Ground
3. EN_N. Active-low enable
4. OUT. Output
5. VCC. Supply

Trace · ratsnest · Drag a part or via. Drag a trace end to edit it. Drag empty board to pan.

Pass at 70. Check previews. Submit records.

Routing6

ConnectivityNot checked
Scored · 35 pts
A net that is split or shorted is not a finished route.
Trace widthNot checked
Scored · 10 pts
The board has to be manufacturable at the default design rules.
ClearanceNot checked
Scored · 10 pts
The board has to be manufacturable at the default design rules.
Copper to edgeNot checked
Scored · 10 pts
The board has to be manufacturable at the default design rules.
J1 zoneNot checked
Scored · 10 pts
The input connector has to sit in the left placement zone.
J2 zoneNot checked
Scored · 10 pts
The output connector has to sit in the right placement zone.

Board2

Route lengthNot checked
Scored · 10 pts
A much longer route than the direct pad path wastes the board.
Via countNot checked
Scored · 5 pts
This board can be finished with a handful of vias.

PCBGrade

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